The Critical Path Problem in Timing Veri

This paper is an introduction to the problem of Critical Path determination in the context of Timing Veriication. After correct logic veriication, timing is the next most important concern to be addressed by designers. The speed of a circuit is related to the length of the longest path through which a signal can travel, also known as the longest true path or critical path of the circuit. This paper will focus on the oating mode of operation and will address two main problems, namely the sensitization conditions for a path to be true and the methods that lead to eecient computation of the true delay of a circuit. Included are descriptions of various sensitization conditions in use, explaining its strengths and shortcomings. The relation between these conditions is also established. Finally a method that eeciently computes the circuit delay is presented. A summary of three very relevant papers on the subject is included and several other references are also discussed. Since these three papers are not comprehensive of the eld, we chose to pursue an historic view of the single-vector condition and then explain the contribution of each of the papers.